Power
Voltage Divider
V
kΩ
kΩ
LDO Regulator
V
V
V
Buck Converter (Step-Down)
V
V
mA
kHz
Boost Converter (Step-Up)
V
V
mA
kHz
Reverse Polarity Protection
P-FET Selection
- V_gs(th) must be negative (e.g. -1V to -3V)
- R_ds(on) low — determines voltage drop at load current
- Gate tied to output through 100kΩ pull-down to GND keeps FET on normally
- P-FET: AO3401, DMG2305UX, SI2305DS
- Schottky: BAT54 (SOD-323), SS34 (SMA), B5819W
Flyback Diode (Inductive Load)
Rules
- Place diode directly across the inductive load — not at the switch
- Keep traces short — diode must clamp the spike before it reaches Q1
- Use Schottky for fast switching (motors, PWM). Standard 1N4007 OK for slow relays
- V_r rating must exceed V_supply by 2× minimum
- Relay coil: 1N4007 or 1N4148
- PWM motor: SS34, B5819W, BAV99
Fuse / Polyfuse / eFuse
Fuse
- One-shot — blows and must be replaced
- Select I_hold slightly above max normal current
- Common: 0402/0603 SMD fuses (Littelfuse 0467 series)
- Self-resetting — trips then recovers when cooled
- Slower to trip than a fuse — not for short-circuit protection of ICs
- Good for USB ports, Li battery packs
- Programmable current limit via R_ilim resistor
- Fast response, soft-start, OVP, reverse protection
- Common: TPS25940, NCP380, AP22811
Buck-Boost / SEPIC
When to Use
- V_out can be above or below V_in (e.g. battery 2.5–4.2V → fixed 3.3V)
- Buck-boost inverts polarity — use SEPIC or Ćuk for positive output
- Lower efficiency than dedicated buck or boost
- LTC3115 (buck-boost, 2A)
- TPS63020 (buck-boost, 2A, small)
- LT1533 (SEPIC)
Charge Pump
Use Cases
- Generate negative rail from single supply (op-amp, RS-232)
- Boost small voltages where an inductor is too large (LED drivers, LCD bias)
- Low current only — typical output 10–100mA
- ICL7660 / MAX1044 — V+ to −V inverter
- TC1044S — improved ICL7660
- LM2776 — voltage doubler
- MAX232 — internal charge pump for RS-232 ±10V
Signal / Analog
RC Low-Pass Filter
kΩ
nF
RC High-Pass Filter
kΩ
nF
Op-Amp — Non-Inverting Amplifier
V
kΩ
kΩ
Op-Amp — Inverting Amplifier
V
kΩ
kΩ
Schmitt Trigger
Purpose
- Eliminates noise-induced multiple transitions on slow or noisy signals
- Converts analog signal to clean digital edge
- Hysteresis = V_trip_hi − V_trip_lo
- 74HC14 — hex inverting Schmitt trigger, no external R needed
- 74HC132 — NAND with Schmitt inputs
- Op-amp with positive feedback (as shown above)
Op-Amp Comparator
Op-Amp vs Dedicated Comparator
- Op-amp as comparator: slow, may oscillate on slow-moving inputs — avoid in production
- Dedicated comparator: fast (ns), designed for open-drain output, rail-to-rail
- LM393 — dual, open-collector, 5V or ±15V
- LM339 — quad comparator
- ADCMP601 — fast (4ns), LVDS output
- Add R from output back to (+) input — prevents chatter near threshold
Instrumentation Amplifier
Use Cases
- Amplifying small differential signals in the presence of large common-mode noise
- Bridge sensors (strain gauge, Wheatstone), thermocouple, current shunt
- CMRR — common mode rejection ratio, higher is better (≥80dB typical)
- Single Rgain resistor sets gain on most INA ICs
- G = 1 + 49.4kΩ/Rgain for INA128
- INA128 / INA129 — precision, G=1–10000
- INA219 — with integrated ADC for current sensing
- AD8221 — low noise, medical grade
Anti-Aliasing Filter (ADC Input)
kΩ
nF
Notes
- R also limits ADC input current — keep R ≤ 10kΩ for most MCU ADCs
- Use C0G/NP0 cap for stable frequency response
DAC Output Reconstruction Filter
Purpose
- Removes high-frequency switching artifacts (images) from DAC output
- Set f_c above audio/signal bandwidth but below f_sample/2
- Unity-gain op-amp buffer prevents load from affecting filter frequency
- Required if driving low-impedance loads (speakers, ADC inputs)
- f_c ≈ 20kHz → R=1kΩ, C=8.2nF (use 8.2nF C0G)
Indicators
LED Current Limiting Resistor
V
V
mA
LED PWM Dimming
How It Works
- PWM frequency ≥ 200Hz — above flicker threshold for most uses
- ≥ 1kHz recommended for video/camera use (avoid rolling shutter banding)
- Duty cycle = perceived brightness (linear current, not linear lumens)
- 10–100Ω between MCU pin and gate — limits current spike, slows switching edge
- Add 10–100kΩ pull-down on gate to GND to prevent floating on startup
- V_gs(th) must be < MCU output voltage (3.3V logic: use logic-level FET)
- BSS138, 2N7002, AO3400A — small SMD N-FETs for LED switching
WS2812 / NeoPixel Hookup
Power
- Each LED draws up to 60mA at full white (20mA × R/G/B)
- Add bulk cap (1000µF / 10 LEDs) near power injection point
- Inject power every 50–100 LEDs to avoid voltage drop on data ground
- 300–500Ω series resistor on DIN — prevents ringing and reflections
- Keep wire between MCU and first LED short (< 20cm without resistor)
- WS2812B: 5V data. Use level shifter if MCU is 3.3V, or use SK6812 (3.3V tolerant)
- Arduino: FastLED, Adafruit NeoPixel
- Pi: rpi_ws281x
- RP2040: PIO-based (no DMA needed)
7-Segment Display Driver
Direct Drive (MCU GPIO)
- R per segment = (V_supply − V_f) / I_f (same as LED calc)
- Multiplexed: cycle through digits fast (>100Hz), drive one digit at a time
- Max MCU current per pin: 8–25mA — check datasheet
- MAX7219 — SPI, drives 8 digits, built-in current control
- TM1637 — I2C-like, common in cheap modules
- HT16K33 — I2C, 16-segment support
Switching
N-Channel MOSFET Low-Side Switch
V
mA
Ω
Selection Rules
- V_gs(th) must be < V_gate (use logic-level FET for 3.3V MCU)
- V_ds must exceed V_load supply with margin
- R_gs (100kΩ) pull-down prevents floating gate on startup
- R_g (10–100Ω) slows switching edge, reduces EMI
P-Channel MOSFET High-Side Switch
How It Works
- P-FET turns ON when Gate is pulled LOW (below V_supply − |V_gs(th)|)
- MCU drives gate LOW to enable load, HIGH (or open) to disable
- R_gs ties gate to V_supply — keeps FET OFF when MCU pin is floating
- Use NPN BJT or N-FET to drive P-FET gate — MCU signal switches the driver
- Or use a gate driver IC (e.g. TC4427)
- AO3401 (SOT-23, 4A, 30V) — 3.3V logic compatible
- SI2305DS (SOT-23, 3.1A, 20V)
- FDN340P (SOT-23, 2A, 20V)
BJT Transistor Switch (NPN)
V
mA
Schematic Components
- LOAD — the device being switched: relay coil, motor, solenoid, LED strip, etc. Connected between V_load and the collector
- R_b — base resistor that limits base current; keeps the BJT in saturation so it acts as a closed switch. Calculate with the fields above
- 2N3904 / BC547 — TO-92, 200mA, general purpose
- MMBT3904 — SOT-23 version of 2N3904
- 2N2222 — TO-92, 600mA
Relay Driver
Design Steps
- Find relay coil resistance from datasheet → I_coil = V_coil / R_coil
- R_b = (V_mcu − 0.7) / (I_coil / hFE × 5) — 5× saturation margin
- D1 flyback across coil: 1N4007 (slow relays) or Schottky (fast PWM)
- Add 100nF bypass cap close to coil terminals
- ULN2003 / ULN2803 — Darlington array, built-in flyback diodes, 500mA/ch
- TD62083 — ULN2003 equivalent, 8-channel
- COIL — the relay coil winding; current through it energizes the mechanical contacts. Connected between V_coil (+) and the collector
- D1 — flyback (freewheeling) diode placed in reverse across the coil. When Q1 turns off, the collapsing magnetic field drives a voltage spike; D1 clamps it and recirculates the energy safely. Cathode to V_coil (+), anode to collector
- R_b — base resistor that limits base current and drives Q1 into saturation, ensuring the collector-emitter looks like a closed switch. Calculate with the formula above
Solid State Relay (SSR)
Advantages over Mechanical
- No moving parts — silent, millions of cycles, fast switching
- No flyback spike on control side (optical isolation)
- Safe for AC mains switching from MCU
- SSRs dissipate ~1W per amp — always use heatsink for loads > 5A
- Check V_drop(on) × I_load for thermal dissipation
- Fotek SSR-25DA — 25A AC, 3–32V DC control (popular, many clones)
- For DC loads: use MOSFET instead — SSRs for AC mains
- R_ctrl — series resistor on the control side that limits current through the internal LED/optocoupler. Typical 330 Ω–1 kΩ depending on V_mcu and target drive current (~10 mA)
- SSR (+) / SSR (−) — DC control input terminals (3–32 V typical). The dashed centre line represents the optical isolation barrier; no electrical connection exists between control and load sides
- L_in / L_out — load-side terminals that switch the high-voltage/high-current circuit (AC mains or DC). Current flows L_in → SSR → L_out when the control side is energised
Motor Control
DC Brushed Motor — H-Bridge
Common Driver ICs
- DRV8833 — dual H-bridge, 1.5A/ch, 2–10V, sleep mode
- TB6612FNG — dual H-bridge, 1.2A/ch, 15V
- L298N — through-hole, 2A, 46V (old, inefficient — avoid for new designs)
- DRV8874 — single H-bridge, 5A, integrated current sense
- Add 100nF ceramic caps directly at motor terminals — suppresses brush noise
- Bulk cap (100–1000µF) near driver V_motor pin
- Never drive both high-side and low-side on same leg simultaneously — shoot-through
- Q1 / Q2 (HS) — high-side switches connecting V_motor to each motor terminal. Typically P-FETs or N-FETs with a bootstrap gate driver. Controlled by HS_A and HS_B signals
- Q3 / Q4 (LS) — low-side N-FET switches connecting each motor terminal to GND. Controlled by LS_A and LS_B signals
- M — the DC brushed motor. Current flows left-to-right (forward) when Q1+Q4 are ON, right-to-left (reverse) when Q2+Q3 are ON
- Midpoints (A/B) — the nodes between each high-side and low-side switch. This is where the motor terminals connect; the junction dots indicate all three paths share the same node
Stepper Motor — A4988 / DRV8825
V
Ω
Current Limit (A4988)
- I_trip = V_ref / (8 × R_sense) for A4988
- I_trip = V_ref / (5 × R_sense) for DRV8825
- Set V_ref with a trimmer — measure at VREF pin with DMM
- Must be placed directly at VMOT/GND pins — protects driver from back-EMF spikes
- V_logic — 3.3 V or 5 V logic supply for the IC control circuitry (VDD pin). Separate from motor voltage
- V_motor / 100µF — motor supply voltage (8–35 V for A4988). The 100 µF electrolytic cap must sit directly at the VMOT/GND pins — it absorbs back-EMF spikes when motor coils switch and will destroy the driver if omitted
- STEP — each rising edge advances the motor one microstep. Pulse width ≥ 1 µs
- DIR — sets rotation direction (HIGH = one way, LOW = the other)
- EN — active-LOW enable; pull HIGH to de-energise coils and reduce heat when idle
- MS1/2/3 — microstepping resolution select pins (full, half, quarter … up to 1/16 or 1/32 step)
- Coil A (1A+, 1A−) — one winding of the bipolar stepper motor. Polarity is reversed to step the rotor
- Coil B (2A+, 2A−) — second winding, driven 90° out of phase with Coil A to produce smooth rotation
BLDC / Brushless — ESC PWM
Arming Sequence
- Send minimum throttle (1ms pulse) for 2s on power-up before ESC arms
- Most ESCs will beep to confirm armed state
- Most ESCs include a 5V BEC on the signal connector — can power MCU
- Do not connect BEC power if MCU has its own supply — disconnect red wire
- Arduino: Servo.h (same PWM as servo)
- Pi: pigpio (hardware PWM on GPIO18)
- MCU_PWM — single PWM signal wire (signal/white/yellow on connector). 50 Hz, 1.0 ms pulse = arm/minimum throttle, 2.0 ms = full throttle
- V_bat — main battery supply into the ESC power leads (red wire). The ESC's internal power stage runs directly from this
- GND — shared ground between MCU, ESC, and battery. Must be a single common ground — floating grounds cause erratic operation
- ESC — Electronic Speed Controller. Converts the MCU PWM signal into 3-phase drive for the BLDC motor, handling all high-current switching internally
- U / V / W — the three phase wires to the BLDC motor. Order sets spin direction — swap any two to reverse
- BLDC Motor — Brushless DC motor. Requires 3-phase commutation from the ESC; cannot be driven directly from a GPIO
Servo PWM Control
deg
Notes
- Pulse width range varies by servo — check datasheet (some: 0.5ms–2.5ms)
- Never power servo from MCU 3.3V pin — use separate 5V supply
- Add 100µF cap on servo supply to suppress current spikes
- MCU_PWM → SIG — PWM signal wire (orange/yellow on 3-pin connector). 20 ms period (50 Hz); pulse width 1.0–2.0 ms sets shaft position. Logic-level — no series resistor needed for most servos
- V_servo → PWR — servo power supply, typically 4.8–6 V (red wire). Must come from a dedicated supply capable of the servo's stall current (0.5–3 A). Never use the MCU 3.3 V rail
- GND — common ground shared between MCU and servo supply (brown/black wire). If servo supply is separate, its GND must still connect to MCU GND
- Servo Motor — contains a DC motor, gearbox, position sensor (potentiometer), and control circuit. The internal controller reads the PWM pulse width and drives the motor to the corresponding angle
Motor Back-EMF Protection
Why It Matters
- Motors generate voltage spikes when switching — can destroy driver ICs and MCUs
- Long motor wires increase inductance → larger spikes
- Capacitors across motor terminals absorb brush noise (RF interference)
- Stepper: 100µF electrolytic directly at VMOT/GND — mandatory, not optional
- Stepper: TVS diode on VMOT if motor wires are longer than ~30 cm
- BLDC/ESC: bulk cap on battery leads close to ESC; ferrite bead on PWM signal wire if noise causes glitches
- M — brushed DC motor, modelled as an inductor. When the switch opens the collapsing magnetic field drives M− above V_motor, producing the destructive spike
- D1 (1N4007) — flyback (freewheeling) diode placed in reverse-parallel across the motor. Cathode to V_motor (+), anode to M−/SWITCH node. Clamps the inductive spike by recirculating current back through the supply. Use 1N4007 for slow switching, Schottky (e.g. 1N5819) for PWM / fast switching
- SWITCH — the low-side FET, BJT, or H-bridge that controls motor current. The spike occurs the instant this opens
- C1 (100 nF) — ceramic snubber cap across M+/M− (shown in schematic). Absorbs high-frequency brush noise and reduces radiated EMI. Add additional 100 nF caps from M+ to chassis and M− to chassis for full suppression
Timers
555 Astable Oscillator
Schematic Components
- V_cc — supply rail tied to pin 8 (Vcc) and pin 4 (RST)
- Ra — timing resistor from V_cc to DIS (pin 7); sets charge path
- Rb — timing resistor from DIS (pin 7) to THR/TRG (pins 6/2); sets both charge and discharge paths
- C — timing capacitor from THR/TRG node to GND; charges through Ra+Rb, discharges through Rb only
- OUT (pin 3) — square wave output; f = 1.44 / ((Ra + 2·Rb) × C)
- CV (pin 5) — control voltage; bypass to GND with 10nF ceramic if unused
kΩ
kΩ
nF
555 Monostable (One-Shot)
Schematic Components
- V_cc — supply rail to pin 8 (Vcc) and pin 4 (RST)
- R — timing resistor from V_cc to DIS (pin 7) / THR (pin 6) node; charges C during output HIGH
- C — timing capacitor; charges to 2/3 V_cc to end pulse
- TRIG (pin 2) — active LOW pulse starts the one-shot; must return HIGH before next trigger
- OUT (pin 3) — goes HIGH for t = 1.1 × R × C, then returns LOW
- CV (pin 5) — bypass with 10nF ceramic to GND if unused
kΩ
µF
RC Delay / Power-On Reset
Schematic Components
- V_cc — supply rail feeds R top
- R — series resistor; limits charge current into C
- C — capacitor to GND; voltage rises exponentially from 0 to V_cc
- RESET_pin — tap between R and C; reaches ~50% V_cc at t ≈ 0.7 × R × C
kΩ
µF
Better Option
- Dedicated supervisor ICs (MCP100, MAX809) give precise, temperature-stable reset
- RC delay is sensitive to leakage current and temperature
Watchdog Timer
Schematic Components
- MCU_WDI — MCU toggles this line periodically to prove it is alive
- V_cc / GND — WDT IC supply (typically 1.2–5.5V)
- MAN_RST — optional manual reset input (active LOW); pull HIGH via resistor if unused
- MCU_RST (/RST) — output; asserted LOW if WDI not toggled within timeout period
Internal vs External
- Most MCUs have a built-in watchdog (AVR: WDTO_x, STM32: IWDG) — use it
- External WDT catches cases where the MCU clock fails or the WDT itself hangs
- MAX6369–MAX6374 — pin-selectable timeout (1ms–60s), SO-8
- TPX9500 — 1.6s timeout, SOT-23-5
- MCP1316 — 1% accurate, multiple timeouts
- Toggle WDI pin (or write to WDT register) only after completing all critical tasks
- Never toggle in an ISR or timer — defeats the purpose
Sensors / Data Acquisition
NTC Thermistor Voltage Divider
Schematic Components
- V_ref — reference supply (3.3V or 5V); also sets the divider top-rail voltage
- R_pull — fixed pull-up resistor (10kΩ typical); provides stable top-of-divider voltage
- NTC — negative-temperature-coefficient thermistor; resistance decreases as temperature rises (10kΩ @ 25°C typical)
- ADC_IN — midpoint voltage fed to MCU ADC; V_out = V_ref × NTC / (R_pull + NTC)
V
kΩ
V
Notes
- Use Steinhart-Hart equation in firmware for accurate temperature from resistance
- β parameter (~3950) from datasheet: T = 1/(1/T₀ + (1/β)·ln(R/R₀))
- 10kΩ pull-up matches common 10kΩ @ 25°C NTC for best sensitivity near ambient
- Place NTC close to heat source; long wires add noise — decouple ADC pin
DS18B20 1-Wire Temperature
Schematic Components
- V_cc — 3.3V or 5V supply to VDD pin
- R (4.7kΩ) — mandatory pull-up resistor from V_cc to DQ line; 1-Wire bus is open-drain and will not function without it
- DQ / MCU_1W — single-wire bidirectional data bus; connects to any MCU GPIO capable of bit-banging
- GND — common ground; in parasite-power mode VDD is also tied to GND
- VDD, GND, DQ — 3-pin TO-92 package
- 4.7kΩ pull-up on DQ to VDD is mandatory
- Multiple sensors share one bus (each has unique 64-bit ROM address)
- OneWire + DallasTemperature libraries (Arduino)
- 12-bit resolution = 0.0625°C steps; conversion takes ~750 ms
- Range: −55°C to +125°C; ±0.5°C accuracy from −10 to +85°C
BME280 I²C (Temp / Pressure / Humidity)
Schematic Components
- V_cc — 3.3V supply to VCC pin; add 100nF decoupling cap close to pin
- R (4.7kΩ) × 2 — I²C pull-up resistors on SCL and SDA; required for bus to work
- SCL → SCK — I²C clock line from MCU to BME280 serial clock input
- SDA → SDI — I²C data line from MCU to BME280 serial data input
- SDO — address select: tie to GND for 0x76, to V_cc for 0x77
- CSB — chip select / mode: tie to V_cc to select I²C mode (vs SPI)
- 100 nF decoupling cap on VCC, close to pin
- Do not use in forced-convection or direct sunlight — self-heating error
- Bosch provides compensation formulas; use Adafruit or official library
- Also available as BMP280 (no humidity), BMP388 (higher precision)
MPU-6050 I²C IMU (Accel + Gyro)
Schematic Components
- V_cc — 3.3V supply; add 100nF + 10µF decoupling caps close to VCC pin
- R (4.7kΩ) × 2 — I²C pull-up resistors on SCL and SDA
- SCL / SDA — I²C bus; max 400kHz Fast mode
- AD0 — address select: tie to GND for 0x68, to V_cc for 0x69
- MCU_INT / INT — optional interrupt output; fires on new data, motion detect, or free-fall event
- 100 nF + 10 µF decoupling on VCC; 4.7kΩ pull-ups on SDA/SCL
- AD0 high → address 0x69 (use two devices on same bus)
- Built-in DMP (digital motion processor) for quaternion output
- Max I²C: 400 kHz fast mode
- Gyro full-scale: ±250/500/1000/2000 °/s configurable
LDR / Photodiode Light Sensor
Schematic Components
- V_ref — supply rail; top of the voltage divider
- LDR — light-dependent resistor; dark ≈ 1MΩ, bright ≈ 1kΩ (varies by part)
- R (10kΩ) — pull-down resistor; choose near geometric mean of LDR min/max for best sensitivity range
- ADC_IN — midpoint voltage; high in dark, low in bright light
- LDR: choose pull-down R near geometric mean of min/max LDR resistance
- Photodiode in reverse-bias gives faster response and better linearity than LDR
- Add 100 nF cap at ADC pin to filter high-frequency noise
Current Sense — Shunt + INA219
Schematic Components
- R_s (R_shunt) — low-value sense resistor in series with the load; voltage across it = I × R_s
- IN+ / IN− — differential inputs measuring voltage across R_shunt; IN+ connects to V+ side (higher potential)
- LOAD — the device being powered; connects between IN− and the return rail
- SCL / SDA — I²C bus to MCU; address 0x40–0x4F set by A0/A1 pins
A
V
Notes
- INA219 max shunt voltage: 320 mV; typical target 100 mV for good SNR
- Low R_shunt = lower drop but less resolution; balance with I²C gain setting
- Calibration register sets LSB current: see Adafruit library or datasheet
Hall Effect Switch
Schematic Components
- V_cc — 3.3V or 5V supply; add 100nF decoupling cap at Hall IC VCC pin
- R (10kΩ) — pull-up on OUT line; required since OUT is open-collector (floats high-Z when no field)
- OUT → GPIO — output pulls LOW when south pole is detected; returns HIGH (via pull-up) otherwise
- GND — common ground for Hall IC
- A3144 / SS411: unipolar — triggers on S pole only, open-collector output
- SS49E: linear analog output — use with ADC for field strength measurement
- Keep sensor away from motor magnets and power traces
- 100 nF decoupling between VCC and GND at sensor
Capacitive Touch (1 MΩ method)
Schematic Components
- 1MΩ — series resistor between MCU_PIN_A (drive) and MCU_PIN_B (sense); limits charge current and sets sensitivity
- Touch Pad — copper pad or wire; human touch adds 10–100pF body capacitance to MCU_PIN_B, slowing RC charge time
- MCU_PIN_A — output pin that drives HIGH to start each charge cycle
- MCU_PIN_B — input pin that measures time for line to reach logic-HIGH threshold
- Pin A drives high; Pin B measures charge time via RC delay
- Human touch adds ~10–100 pF → measurably longer charge time
- Arduino CapacitiveSensor library handles timing automatically
- 1 MΩ provides ESD protection and sets sensitivity
- Shield surrounding traces reduces noise; ground pour improves baseline
- Works through up to ~5 mm of acrylic or PCB laminate
Microcontroller Support
Decoupling Cap Layout
Schematic Components
- C1 (100nF, X7R/X5R) — high-frequency bypass cap; place <1mm from IC VCC pin, 0402 or 0603 for lowest parasitic inductance
- C2 (10µF) — bulk cap for mid-frequency demand spikes; place near regulator output, one per IC or power domain
- GND via — return path must be as short as C1's own trace; via directly below the cap, no stub
- 100 nF per VCC pin — handles high-frequency switching noise
- 10 µF bulk per IC or regulator — handles mid-frequency demand spikes
- Place cap closer to pin than via; keep return path short
- Use 0402 or 0603 for lowest parasitic inductance
- Avoid Y5V/Z5U dielectrics — capacitance drops 80% at rated voltage
Crystal Oscillator + Load Caps
Schematic Components
- XTAL — quartz crystal; connects between MCU_XTAL1 and MCU_XTAL2 pins; frequency sets system clock
- CL1 / CL2 — external load capacitors; each = 2 × C_load − C_stray; matched pair from pin to GND
pF
pF
Notes
- Short traces (<5 mm), away from noisy signals; guard ring optional
- Do not route other signals under crystal — parasitic coupling
- TCXO/OCXO when accuracy < ±10 ppm required (GPS, BLE)
Reset Circuit (RC + Supervisory IC)
Schematic Components
- R (10kΩ) — pull-up from V_cc to /RESET; charges C through R after power-on
- C (100nF) — holds /RESET low during power-up ramp; t_delay ≈ R × C ≈ 1ms
- /RESET — active-low reset input on MCU; must be held below logic-low threshold for at least t_reset (see datasheet)
- RC: unreliable for slow power-up ramps — VCC may be in brown-out zone too long
- Supervisory ICs hold reset until VCC is stable above threshold (e.g. 2.93 V)
- Manual reset: add momentary switch from /RESET to GND with 100 Ω series resistor
Boot Mode Selection
Schematic Components
- R (10kΩ) — pull-up keeps BOOT0 HIGH (flash boot) in normal operation
- SW — push-button from BOOT0 to GND; hold during reset to enter bootloader
- BOOT0 — STM32 boot mode pin; sampled at reset edge; HIGH = system memory / UART bootloader
- STM32: BOOT0=1, BOOT1=0 at reset → system memory (UART bootloader)
- Pull BOOT0 low (GND) for normal flash boot; add header for field access
- ESP32: GPIO0 low at reset → download mode (uses built-in USB-UART bridge)
- Add 0 Ω jumper pads for production vs development configuration
SWD / JTAG Debug Header
Schematic Components
- Pin 1 — VCC — target 3.3V reference; square pad for orientation; allows debugger to sense target voltage
- Pin 2 — SWDIO — bidirectional serial data; 100Ω series resistor near header for ESD protection
- Pin 4 — SWCLK — serial clock from debugger; 100Ω series resistor
- Pin 6 — SWO — optional serial wire output (ITM trace); leave NC if trace not used
- Pins 3, 5 — GND — common ground
- J-Link, ST-LINK, CMSIS-DAP all support SWD
- 100 Ω series on SWDIO/SWCLK at header — protects against shorts
- Tag-Connect saves board space — pogo pin footprint, no connector
- JTAG needs 4 wires (TMS, TCK, TDI, TDO) — use for older cores or chain
ISP Header (AVR)
Schematic Components
- Pin 1 — MISO — Master In Slave Out; data from AVR to programmer; square pad
- Pin 2 — VCC — target supply reference for programmer level-sensing
- Pin 3 — SCK — SPI clock from programmer; 100Ω series near header
- Pin 4 — MOSI — Master Out Slave In; data from programmer to AVR
- Pin 5 — RST — active-low reset; programmer pulls low to enter ISP mode; needs 10kΩ pull-up to VCC on target
- Pin 6 — GND — common ground
- 100 Ω series resistors on SCK/MOSI/MISO — isolate from in-circuit SPI devices
- RST line needs 10kΩ pull-up to VCC; 100 nF cap optional (may interfere with programming)
- Fuse bits set clock source, BOD, EEPROM preserve — be careful, easy to brick
Communication / Interface
UART Level Shift (3.3V ↔ 5V)
Schematic Components
- TXB0102 — bidirectional 2-bit voltage-level translator with auto-direction sensing; no DIR control pin required
- VCCA — 3.3V supply to low-voltage (A) side
- VCCB — 5V supply to high-voltage (B) side
- OE — output-enable pin; tied HIGH to VCCA to permanently enable translation
- A1 — 3.3V-side bidirectional signal pin connected to 3.3V MCU UART
- B1 — 5V-side bidirectional signal pin connected to 5V device UART
- R1 (1kΩ) — series resistor in resistor-divider path (5V TX → 3.3V RX)
- R2 (2kΩ) — shunt resistor to GND; with R1 divides 5V → 3.3V on 3.3V_RX net
- 3.3V TX → 5V RX usually works directly (5V UART sees 3.3V as logic high)
- 5V TX → 3.3V RX needs level shift — resistor divider or TXB0102
- TXB0102 handles up to 1 MHz; for SPI/I2C use TXS0108 or MOSFET shifter
USB Full-Speed D+/D− (RP2040)
Schematic Components
- RP2040 — microcontroller with integrated USB Full-Speed (12 Mbps) PHY; no external USB transceiver needed
- R_dp (27Ω) — series resistor on USB_DP line; limits edge rate and matches impedance per USB 2.0 spec
- R_dm (27Ω) — series resistor on USB_DM line; matched to R_dp, same net rules apply
- USB Connector — USB-C or Micro-B receptacle; D+ and D− must route as 90Ω differential pair with matched length (<50 mm)
- D+ (internal 1.5kΩ pull-up) — RP2040 enables this pull-up to signal Full-Speed device during enumeration
- 27 Ω series resistors are USB spec for signal integrity — do not omit
- Route D+/D− as differential pair: same length, <50 mm, away from clocks
- No via on D+/D− traces if avoidable; use 4-layer board for best results
- Decoupling: 100 nF + 10 µF on USB VBUS, TVS diode on VBUS and D lines
USB-C Power Delivery (PD Sink)
Schematic Components
- USB-C Connector — carries VBUS, CC1, CC2, D+, D−, GND; use a mid-mount or top-mount receptacle with shield tied to chassis GND
- R_cc1 (5.1kΩ) — CC1 pull-down resistor to GND; signals to USB-C charger that this is a sink (powered device)
- R_cc2 (5.1kΩ) — CC2 pull-down resistor to GND; both CC lines must be terminated; 5.1kΩ requests up to 3A at 5V
- VBUS_IN — power input net from charger; add TVS diode (PRTR5V0U2X) and bulk capacitor (10µF + 100nF) here
- DATA_DP / DATA_DM — optional USB 2.0 data lines; leave unconnected for power-only sink
- 5.1 kΩ on CC lines tells USB-C charger to supply 5V/900mA or 5V/1.5A/3A
- For 9V/12V/20V PD negotiation, a PD controller IC is required
- HUSB238: standalone PD sink, no MCU needed, sets voltage via resistors
- TVS on VBUS; protect D+ and D− with ESD array
SPI Bus (MOSI / MISO / SCK / CS)
Schematic Components
- MCU — SPI controller; drives MOSI, SCK, and CS lines; samples MISO
- MOSI — Master Out Slave In: data from MCU to device; shared bus wire
- MISO — Master In Slave Out: data from device to MCU; shared bus wire; add 10kΩ pull-up if multiple devices to prevent float when CS deasserted
- SCK — Serial Clock: shared by all devices on the bus
- CS0 / CS1 — Chip Select: active-LOW, one dedicated line per device; never share CS between devices
- SPI Dev 1 — example peripheral (sensor, display, ADC); mode (CPOL/CPHA) must match MCU configuration
- Each device needs its own CS line; do not share CS
- CPOL and CPHA must match device datasheet (Mode 0 most common)
- Terminate long traces (>10 cm at >10 MHz) with 33 Ω series near driver
- Decouple each device VCC; MISO floats when CS deasserted — add pull-up if bus-sharing
I²C Bus (Pull-Up Resistors)
Schematic Components
- R_sda (4.7kΩ) — SDA pull-up resistor from 3.3V rail to SDA bus; bus is open-drain — this resistor is mandatory
- R_scl (4.7kΩ) — SCL pull-up resistor from 3.3V rail to SCL bus; lower value for higher speeds
- SDA bus — bidirectional open-drain data line; all devices share this wire
- SCL bus — clock line driven by MCU (controller); all devices share this wire
- Device 1 / Device 2 — I²C peripherals each with unique 7-bit address; use TCA9548A multiplexer for address conflicts
V
Notes
- Too high R → slow rise time, corrupt at high speed; too low → excess current + drive issues
- Multiple devices share SDA/SCL; each needs unique 7-bit address
- I2C address conflicts: use TCA9548A multiplexer to expand bus
RS-485 Half-Duplex Transceiver
Schematic Components
- MAX485 — half-duplex RS-485 transceiver IC; 3.3V or 5V supply; SP3485 is direct 3.3V equivalent
- DI — Driver Input: connected to MCU TX; data transmitted onto the bus when DE=HIGH
- RO — Receiver Output: connected to MCU RX; data received from bus when /RE=LOW
- DE + /RE — tied together and driven by MCU DIR pin; HIGH=transmit, LOW=receive
- A / B — differential bus lines to twisted-pair cable; A is non-inverting, B is inverting
- 120Ω termination — resistor between A and B at each cable end to match characteristic impedance and suppress reflections
- Half-duplex: set DIR high to transmit, low to receive (avoid bus contention)
- 120 Ω termination at both cable ends — match cable impedance (~120 Ω for Cat5)
- Bias resistors (560 Ω to VCC on A, 560 Ω to GND on B) define idle state
- Supports up to 32 nodes, 1200 m cable, 10 Mbps max
CAN Bus (TJA1050 Hookup)
Schematic Components
- TJA1050 — 5V CAN bus transceiver IC; interfaces MCU CAN peripheral to CANH/CANL differential bus
- TXD / RXD — logic-level interface to MCU CAN peripheral (UART-like timing, CAN framing)
- STB (standby) — pull to GND for normal operation; pull HIGH to put transceiver in low-power standby
- CANH / CANL — differential bus lines; dominant bit: CANH>CANL; recessive: CANH≈CANL≈2.5V
- 120Ω termination — required at both physical ends of the bus only (not at intermediate nodes)
- Split termination — 60Ω + 60Ω with 4.7nF to GND at center tap improves EMI rejection
- TJA1050 is 5V; for 3.3V MCU use TJA1051T/3 or SN65HVD230 (3.3V)
- Max speed 1 Mbps; up to 40 nodes on one bus
- CAN FD (ISO 11898-2): up to 8 Mbps data phase — use MCP2518FD + ATA6563
- 120 Ω termination resistors required at bus ends, not at intermediate nodes
1-Wire Bus
Schematic Components
- R_pull (4.7kΩ) — mandatory pull-up from V_cc to DQ bus; bus is open-drain and will not function without it
- DQ bus — single-wire bidirectional data line; carries both parasitic power and data
- MCU_GPIO — any general-purpose I/O pin with open-drain mode; bit-bang or hardware 1-Wire peripheral
- Dev 1–3 (DS18B20) — 1-Wire temperature sensors; VCC pin can be powered from DQ (parasite mode) or wired to V_cc
- Strong pull-up — external MOSFET pulling DQ to V_cc required during DS18B20 12-bit temperature conversion (~750 ms) to supply conversion current (>1 mA)
- Single wire carries power (parasite mode) and bidirectional data
- 4.7 kΩ pull-up required; strong pull-up (MOSFET to VCC) needed during DS18B20 conversion
- Each device has unique 64-bit ROM address — no address conflicts
- Works up to ~100 m with proper termination; speed ~16 kbps standard
RF / Radio
50Ω Microstrip Trace
Schematic Components
- Trace (W) — copper signal trace on PCB surface; width W determines characteristic impedance Z₀
- Dielectric (h, εr) — PCB substrate between trace and ground plane; FR4 εr≈4.4, h=1.6mm (2-layer board)
- GND plane — solid uninterrupted copper pour below the signal trace; must have no cuts or splits
- Via fence — row of GND vias ≤λ/20 spacing along both sides of trace to confine fields and reduce crosstalk
mm
Ω
Notes
- Thinner dielectric → narrower trace; use controlled-impedance stackup for RF
- Keep ground plane solid under RF traces; no splits or cuts
- Via fencing: row of GND vias ≤ λ/20 spacing along both sides of trace
Via Fence (GND Stitching)
Schematic Components
- GND vias — through-hole or blind vias with pads connected to the GND copper pour; row runs parallel to the RF trace on both sides
- s (spacing) — centre-to-centre distance between consecutive vias along the fence; must be ≤ λ_eff/20 at the highest operating frequency
- d (distance) — from via centre to nearest edge of the RF trace; keep ≤ λ_eff/8; too close couples noise, too far loses shielding
- GND plane — solid copper pour on the reference layer; all via pads connect to it — no splits or islands
GHz
Notes
- Typical via: 0.3 mm drill, 0.6 mm pad — fits comfortably alongside a 50Ω microstrip
- Fence both sides of the trace; a single-sided fence only halves the leakage
- Use same fence rules for board-edge guard rings around RF modules
- At 2.4 GHz on FR4: s_max ≈ 4.4 mm, d_max ≈ 11 mm
RF Bias-T (Active Antenna)
Schematic Components
- FB (Ferrite bead) — high impedance at RF (e.g. 220Ω @ 100MHz, BLM21PG221SN1); passes DC, blocks RF from entering DC supply
- ANT PORT — bias-T combined node: active antenna connects here, receives both DC power and carries RF signal
- C_bypass (100nF) — RF bypass shunt to GND at ANT node; low impedance at RF to shunt RF away from DC supply path
- C_block (100nF) — DC blocking capacitor in series with RF receiver path; passes RF signal, blocks DC bias voltage
- RF_OUT — clean RF signal to MCU receiver input or SDR, with DC removed by C_block
- Ferrite bead blocks RF from entering DC supply; cap blocks DC from RF path
- Use for GPS active antennas (typically 3–5V, 5–20 mA LNA)
- Place bias-T components as close to antenna port as possible
- Check LNA voltage on antenna datasheet — some are 3.3V, others 5V
SMA / U.FL Connector Hookup
Schematic Components
- SMA Center Pin (RF) — 50Ω coaxial connector center conductor; route 50Ω controlled-impedance trace directly to IC RF pin with no vias if possible
- SMA Shell (GND) — outer shield connected to GND plane via 4+ vias directly beneath connector; do not skimp on via count
- U.FL Center — miniature coaxial connector (also called IPEX or MHF); route 50Ω trace to IC; keep trace <10mm
- U.FL Shell (GND) — GND vias must be within <1mm of shell pad to maintain coaxial transition integrity
- Pigtail cable — U.FL to SMA pigtail brings internal U.FL connector out to panel-mount SMA for external antenna connection
- SMA rated to 18 GHz; SMA-RP (reverse polarity) for WiFi antennas
- U.FL: small, fragile, rated ~30 mating cycles — use for internal connections
- Ground the shell with 4+ vias directly to ground plane
- Minimize trace length between IC and connector — every mm matters at 2.4 GHz+
LoRa Module (RFM95 / SX1276 SPI)
Schematic Components
- RFM95W (SX1276) — LoRa transceiver module; 3.3V, SPI interface, 868/915 MHz ISM band
- SCK / MOSI / MISO / NSS — SPI bus; add 100nF decoupling on 3.3V pin; NSS is active-LOW chip select
- DIO0 — interrupt output from module; signals TX done or RX done; connect to MCU GPIO with interrupt capability
- RESET — active-LOW reset; pulse LOW ≥100µs on power-up for reliable initialization
- ANT (50Ω) — connect via 50Ω trace to SMA or quarter-wave wire antenna; never transmit without antenna connected
- Quarter-wave antenna: 868 MHz → 86 mm wire; 915 MHz → 82 mm
- 100 nF + 10 µF decoupling on VCC; keep antenna away from MCU clock traces
- Use RadioLib or LMIC library; set frequency/SF to match region (EU 868, US 915)
- Do not transmit without antenna connected — reflected power damages PA
WiFi / BT Module (ESP32 Antenna Keepout)
Schematic Components
- ESP32 Module — WiFi/BT SoC module with PCB trace antenna or U.FL connector; 3.3V, 250mA peak current
- Antenna Keepout Zone — no copper (signal, power, or GND) allowed within the zone defined in the Espressif module datasheet; minimum 3mm clearance from PCB edge
- EN pin — chip enable; pull HIGH via 10kΩ; add RC (10kΩ + 1µF) between EN and GND for reliable power-on reset
- Decoupling — 10µF + 100nF per VDD pin, placed directly adjacent to module power pins
- Boot strapping pins — GPIO0, GPIO2, GPIO15 affect boot mode; avoid pulling these during startup
- Espressif datasheet specifies antenna keepout area — strictly follow it
- Place bulk decoupling (10 µF) + 100 nF per VDD pin, near module
- EN (chip enable) pin: pull up 10kΩ; add RC (10kΩ + 1µF) for reliable power-on reset
- GPIO0, GPIO2, GPIO15 have boot-mode effects — avoid strapping during startup
Antenna Matching Pi Network
Schematic Components
- C1 (12pF shunt) — input shunt capacitor from PA_OUT node to GND; part of impedance transformation from Z_source
- L (68nH series) — series inductor between C1 and C2 nodes; provides inductive reactance for impedance transformation
- C2 (12pF shunt) — output shunt capacitor from L output node to GND; completes π topology to match Z_load (antenna)
- Q factor — Q = √(Z_high/Z_low − 1); higher Q gives narrower bandwidth and better harmonic rejection
- 0402 RF components — use high-Q inductors (Q>30) and ±0.1pF NP0/C0G capacitors; verify with VNA after assembly
- Pi network transforms impedance and filters harmonics simultaneously
- Use Smith chart or online RF calculator to solve C/L for Z_s → Z_load
- Q factor determines bandwidth: Q = √((Z_high/Z_low) − 1)
- Use 0402 RF-grade components (±0.1 pF caps, high-Q inductors)
Protection / EMI
ESD Protection (TVS + Series R)
Schematic Components
- EXT_SIG — external signal entering the board (connector pin exposed to user or cable); ESD events arrive here
- R_series (33Ω) — current-limiting resistor between external signal and TVS/IC; limits peak current during ESD event; 33–100Ω typical for UART/GPIO
- TVS (bidirectional) — Transient Voltage Suppressor; clamps overvoltage to safe level in both polarities; e.g. PRTR5V0U2X for 5V clamping
- IC_PIN — protected signal arriving at IC input; voltage clamped to TVS breakdown level by the time it gets here
- C_j (junction capacitance) — TVS adds parasitic capacitance; choose low-C TVS (<0.5pF) for USB or high-speed signals
Notes
- Place TVS at board edge, before any other circuitry
- Series R limits current into TVS and IC; 33–100 Ω typical for UART/GPIO
- PRTR5V0U2X: dual-line, 0201, 5V clamping — common for USB data lines
- ESD rating: IEC 61000-4-2 Level 4 = ±8 kV contact, ±15 kV air
- TVS C_j adds capacitance — use low-C TVS (<0.5 pF) for high-speed lines
EMI Filter (Ferrite Bead + Bypass Cap)
Schematic Components
- FB (Ferrite bead) — frequency-dependent resistor; high impedance at RF/switching frequencies, low resistance at DC; e.g. BLM21PG221SN1 (220Ω @ 100MHz)
- C1 (100nF) — high-frequency bypass capacitor; X7R or NP0/C0G; shunts high-frequency noise to GND after the ferrite bead
- C2 (10µF) — bulk bypass capacitor; handles lower-frequency ripple and load transients; X5R or electrolytic
- NOISY VCC / CLEAN VCC — ferrite bead + cap filter isolates analog or sensitive digital supply from noisy digital switching regulator output
Notes
- Ferrite bead is a frequency-dependent resistor — dissipates noise as heat
- Choose bead rated for DC current (check impedance vs current curve)
- Bead + cap forms LC-like filter; resonance can amplify at one frequency — check with SPICE
- Use for isolating ADC/analog supply from digital switching noise
Overvoltage Clamp (Zener)
Schematic Components
- R_series — limits current into Zener and protected IC pin; R = (V_in − Vz) / I_clamp; must dissipate (V_in − Vz) × I_clamp watts
- Zener diode — cathode connects to protected output; anode to GND; clamps output to Vz + Vf ≈ Vz + 0.3V
- PROT_OUT — voltage-clamped output; safe for 3.3V IC input even if V_in spikes above that
- Vz selection — choose Zener breakdown voltage slightly above normal signal voltage (e.g. 3.3V Zener for protecting 3.3V logic pin from 5V signal)
V
V
mA
Notes
- Zener must absorb full overvoltage current — choose wattage accordingly
- TVS diode preferred over Zener for transients (faster response, lower clamping voltage)
Overcurrent Limit (Sense R + Comparator)
Schematic Components
- R_sense (low Ω) — shunt resistor in series with load current path; voltage across it = I × R_sense; Kelvin (4-wire) connection eliminates trace resistance error
- IN+ / IN− — differential sense inputs to INA219; measure voltage drop across R_sense in both directions
- INA219 — I²C current/power monitor IC; 12-bit ADC, programmable gain, 0.1Ω to 0.01Ω sense; I²C address set via A0/A1 pins
- V_sense target — keep ≤100mV across R_sense for reasonable power loss; R_sense = V_sense_max / I_max
- MCU action — read INA219 via I²C; if current exceeds threshold, disable load switch (MOSFET gate) or trigger alert
A
V
Notes
- Lower V_sense = less power loss but harder to measure accurately
- Use INA219 for I²C monitoring + comparator, or dedicated eFuse IC (TPS2596)
- Kelvin (4-wire) connection to sense resistor eliminates trace resistance error
Connectors
JST-PH / JST-SH Pinout
Schematic Components
- JST-PH 2.0mm (2-pin) — standard LiPo battery connector; Pin 1 = + (red), Pin 2 = − (black); Pin 1 is square pad on most boards
- JST-SH 1.0mm (4-pin) — Qwiic (SparkFun) and STEMMA QT (Adafruit) I²C connector; GND/3.3V/SDA/SCL; daisy-chainable between I²C devices
- JST-XH 2.5mm — RC battery balance lead connectors; also used for multi-cell pack monitoring
- Polarity warning — JST polarity is NOT standardized across all manufacturers; always verify with multimeter before connecting
Notes
- Polarity is NOT standardized across manufacturers — verify before connecting
- Adafruit/SparkFun Qwiic use JST-SH 4-pin (I²C + power) for daisy-chaining
- RC LiPo: JST-PH 2-pin for small packs; XT30/XT60 for high-current packs
USB Type-A / B / C Pinout
Schematic Components
- USB Type-A (host) — 4 pins: VBUS(+5V), D−, D+, GND; used on computers and USB hubs as host port
- USB Micro-B (device) — 5 pins: adds ID pin (GND = OTG host, float = device); common on older MCU dev boards
- USB Type-C CC1/CC2 — orientation detection and Power Delivery negotiation pins; 5.1kΩ to GND identifies sink device; 56kΩ to VBUS identifies source
- VBUS protection — add 10µF + 100nF decoupling and TVS diode on VBUS at board entry point
- D+/D− termination — 45Ω each to GND (inside USB device; usually inside the chip)
Notes
- USB-C CC1/CC2: 5.1kΩ to GND for sink (device), 56kΩ to VBUS for source (host)
- VBUS: add 10 µF + 100 nF decoupling; TVS diode for ESD protection
- D+/D− impedance: 45 Ω each to GND for termination inside device
SMA / XT30 / Barrel Jack
Schematic Components
- SMA (RF 50Ω) — center conductor carries RF signal on 50Ω controlled-impedance trace; outer shell connects to GND plane via 4+ vias; rated to 18 GHz
- XT30 (high current) — rated 30A continuous; yellow housing; square tab = positive, round tab = negative; XT60 is 60A version
- Barrel Jack (DC power) — 5.5mm OD / 2.1mm ID most common; center pin typically positive but NOT standardized; verify before connecting
- Reverse polarity protection — add P-channel MOSFET or Schottky diode on barrel jack input; P-FET preferred (near-zero voltage drop)
Notes
- Barrel jack polarity not standardized — verify with multimeter before connecting
- XT30 for <30A; XT60 for <60A; use silicon wire with correct AWG
- Add reverse-polarity protection (P-FET or Schottky) on barrel jack input
RJ45 Ethernet
Schematic Components
- Pins 1/2 (TX+/TX−) — transmit differential pair; Orange/White and Orange; route as 100Ω diff pair, matched length ±100 mil
- Pins 3/6 (RX+/RX−) — receive differential pair; Green/White and Green; note pins 3 and 6 are NOT adjacent — be careful with routing
- Magnetics (transformer + CMC) — mandatory between RJ45 pins and Ethernet PHY chip; provides isolation and common-mode noise rejection
- MagJack — RJ45 with integrated magnetics; simplifies PCB layout; recommended for new designs
- PoE — DC power injected via center taps of magnetics on pairs 1/2 and 3/6 for Power over Ethernet
Notes
- Integrated magnetic RJ45 (MagJack) simplifies layout — magnetics built in
- Route differential pairs together; match length ±100 mil; no 90° bends
- PoE: pins 1/2 and 3/6 carry data + DC power via center taps of magnetics
DB9 RS-232
Schematic Components
- DB9 Male (DTE) — Pin 2 = RX (in), Pin 3 = TX (out), Pin 5 = GND; Pin 7/8 = RTS/CTS flow control
- RS-232 logic levels — +3V to +15V = logic 0; −3V to −15V = logic 1 (inverted from TTL!); never connect directly to 3.3V MCU GPIO
- MAX232 / SP3232 — level-shifter IC; generates ±9V from 3.3V/5V supply using internal charge pump; requires four 1µF caps per datasheet
- SP3232E — 3.3V compatible version; MAX3232 is pin-compatible; both work to 120 kbps
- Null-modem cable — crosses TX/RX (and RTS/CTS) for MCU-to-PC; straight cable for MCU-to-modem/DCE
Notes
- RS-232 levels are inverted relative to TTL: +3V to +15V = logic 0
- MAX232 needs four 1 µF charge-pump caps (check datasheet footprint)
- SP3232E is 3.3V compatible; MAX3232 pin-compatible alternative
- Cable: null-modem (cross TX/RX) for MCU-to-PC; straight for MCU-to-modem
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