Impedance

• Target 90 Ω differential (≈ 45 Ω single-ended each trace). Use your PCB fabricator's controlled-impedance calculator with your copper weight and dielectric.
• Standard 4-layer with 0.1 mm traces on outer layers over a solid GND plane often gives 90–100 Ω differential on FR4.

Length Matching

• Intra-pair — the two traces within a differential pair (e.g. TX1+ and TX1−) must be matched to within ±0.1 mm. Compensate with small meanders on the shorter trace. Keep bends to 45° — never 90°.
• Inter-pair — between different pairs (e.g. TX vs RX for the same port) match to within ±5 mm. This is looser — the host controller tolerates inter-pair skew.

Coupling & Routing

• Route each pair tightly coupled — trace separation ≤ 2× trace width (commonly 0.1 mm traces with 0.1 mm gap). This maintains the differential impedance and reduces EMI.
• Keep upstream SS traces under 25 mm on-PCB. Downstream ports under 25 mm each. The USB 3.2 Gen 1 loss budget is tight; long traces mandate lower-loss dielectric.

4-Layer Recommended Stack

• Layer 1 (top) — signal: USB traces, components
• Layer 2 — solid GND plane, unbroken under all USB traces
• Layer 3 — power plane (3.3V, VBUS fills)
• Layer 4 (bottom) — signal: non-critical routing

Plane Integrity

• No splits under USB traces — any gap or cutout in the GND layer forces the return current to detour, radiating EMI and distorting impedance. Pour the GND plane solid; avoid routing slots under J1–J5 footprints.
• Via transitions — avoid layer-change vias on SS pairs where possible. If unavoidable, place GND stitching vias adjacent to each signal via (within 0.5 mm) so the return path stays local.

Shielding

• Crystal guard ring — surround Y1, C18, C19, and the SSXI/SSXO traces with a GND guard ring connected to GND plane with multiple vias. Keep USB SS traces at least 3 mm away from this area.
• USB connector shell — connect J1 (USB-C) shield to GND through a parallel 1 nF cap + 1 MΩ resistor to board GND. This provides chassis-GND separation while still draining ESD. J2–J5 shells connect to GND directly.

ESD TVS Position

• Place each PRTR5V0U2X within 5 mm of its connector, on the signal path before any other trace routing or vias. Board-edge placement is ideal — the TVS must see the ESD pulse before the IC does.

Decoupling Caps

• Each VCC33 and VCC11 pin on VL817 gets its own 100 nF cap placed within 0.5 mm.
• Add a shared 10 µF bulk cap for each rail within 5 mm. Use X7R ceramic for 100 nF (stable over temperature), X5R for 10 µF.

Polyfuse & Ferrite

• F1 and L1 go in series on VBUS before any branching. Place F1 near the upstream connector J1 to protect all downstream circuitry. L1 goes between F1 and the VCC5I input.

CC Resistors (UFP mode)

• Both CC1 and CC2 require individual 5.1 kΩ pull-down to GND. This identifies the hub as a USB-C UFP (peripheral/device). Without these, many hosts will not enumerate the hub.
• Do not share CC resistors — each pin needs its own. Total two resistors: R1 (CC1) and R2 (CC2).

SuperSpeed Lane Assignment

• USB-C uses TX1±/RX1± for one cable orientation and TX2±/RX2± for the flipped orientation. The VL817 supports only one SS lane — check the datasheet for which side (TX1/RX1 or TX2/RX2) is connected. A CC-based orientation mux IC (e.g. TUSB321) can handle both orientations automatically.
• Cable label convention: TX and RX are from the host perspective. The hub's IC uses the opposite: cable TX1± connects to IC SSRX0± input, cable RX1± connects to IC SSTX0± output.

Ferrite Bead on VBUS

• L1 (600 Ω at 100 MHz, ≥ 500 mA) filters switching noise on the upstream VBUS rail before it reaches VL817's VCC5I input. Place L1 in series between J1 VBUS pin and the bulk cap.

From J1 to VL817 SSRX0± and SSTX0±

• Route TX1± (cable) as a tightly coupled pair to IC SSRXP/SSRXN. Keep the two traces within 0.1 mm length of each other.
• Route RX1± (cable) to IC SSTXP/SSTXN similarly.
• Keep the TX pair and RX pair separated by at least 0.5 mm (3× trace width) to minimise cross-coupling.
• No 90° bends. Use 45° corners or arcs. Never let a high-speed trace run parallel to a neighbouring pair for more than 15 mm without a ground trace between them.
• Place a GND via beside each SS via if you must change layers.

USB 2.0 D+/D− from J1

• Route as a 90 Ω differential pair to VL817 HSD0+ and HSD0−. Length-match within 2 mm (less critical than SS, but still important above 100 MHz).
• If space allows, add optional 33 Ω series resistors R3/R4 between the TVS and IC — these damp reflections from impedance discontinuities at the connector.

Component Roles

• F1 (500 mA polyfuse) — Resettable fuse in series with VBUS. Protects against shorts on the PCB or downstream ports. Reset by removing USB power.
• L1 (ferrite bead) — EMI filter. High-frequency noise on VBUS (from host charger switching) is attenuated before reaching VL817.
• VL817 on-chip regulators — The VL817 integrates a 5V→3.3V LDO and a 5V→1.1V DC-DC switching regulator. No external LDO is needed, but the DC-DC requires a 4.7µH external inductor on the LX pin and a 10µF output cap, plus a feedback resistor network. The LDO output (VCC33O) requires a 4.7µF cap. Supply clean 5V to VCC5I (DC-DC input) and VCC5LDO (LDO input).
• C1–C4 (bypass/bulk caps) — 100 nF + 10 µF on the VCC5I input. 100 nF + 10 µF on VCC33 output pins. 100 nF per VCC11 pin. Required for on-chip regulator stability.

Downstream VBUS Switching

• Each downstream SS port (J2, J3) should have an AP2141 or TPS2051C power switch IC on its VBUS line. These provide overcurrent protection per-port (≈ 500 mA limit), current limiting, and a fault flag the hub controller can read.
• USB 2.0 ports (J4, J5) can use the same switch or a simple polyfuse per port for a lower component-count build.

Current Budget (bus-powered)

• USB upstream provides 500 mA (USB 2.0 host) or up to 900 mA (USB 3.x). With 4 downstream ports active at 100 mA each = 400 mA load plus hub overhead ≈ 50 mA. Total ≈ 450 mA. Keep total downstream allocation under 400 mA for bus-powered designs to leave headroom.

Placement Rules

• The VL817-Q7 QFN-76L has multiple VCC33 and VCC11 pins distributed around the package. Place one 100 nF 0402 cap per power pin, within 0.5 mm of each pin.
• Use short, direct traces from pad to cap to GND. Avoid routing through a via if possible — via inductance degrades the bypass at high frequency.
• The VCC33 and VCC11 rails are generated on-chip — bypass caps connect from the IC output pins to GND, not from an external supply.
• Add one 10 µF 0805 bulk cap per rail (VCC5, VCC33, VCC11) within 5 mm of the IC centre.
• Place the 4.7µH DC-DC inductor (L2) close to the LX pin with a short, wide trace. The 10µF output cap connects between the inductor output and GND — keep this loop area small to minimise switching noise radiation.

Exposed Pad (EP)

• VL817-Q7 QFN-76L has a thermal exposed pad on the bottom. Connect this to the GND plane through a grid of thermal vias (e.g. 3×3 array, 0.3 mm drill). This is both an electrical GND connection and the primary heat path for the IC.

SSREXT Reference Resistor

• The SSREXT pin requires an external precision resistor to GND: 6.04 kΩ ±1%. This sets an internal reference current for the USB PHY analog block. Do not omit or substitute with a standard ±5% value — use a 1% tolerance part.

Firmware / SPI Flash

• VL817 does not use strapping pins for configuration. All settings (port mode, power mode, VID/PID, charging behaviour) are stored in an external SPI flash and loaded at power-on. The SPI flash is required — without it the IC will not enumerate.
• Without a custom EEPROM image, the hub enumerates with VIA Labs' default VID 0x2109, PID 0x0817. Flash the IC using the VIA Labs hub configuration tool over USB, or with a CH341A programmer offline.

9-Pin USB Type-A Pinout

• Pin 1: VBUS (5V, switched by AP2141)
• Pin 2: D−
• Pin 3: D+
• Pin 4: GND
• Pin 5: SS_RX− (StdA_SSRX−, cable view)
• Pin 6: SS_RX+ (StdA_SSRX+)
• Pin 7: GND_DRAIN (separate SS shield drain)
• Pin 8: SS_TX− (StdA_SSTX−)
• Pin 9: SS_TX+ (StdA_SSTX+)
• Shell: Chassis GND — connect directly to board GND pour

Routing to VL817

• SS_RX± of connector → VL817 SSTXn+/SSTXn− (port n output). Again: connector-side RX is IC-side TX.
• SS_TX± of connector → VL817 SSRXn+/SSRXn− (port n input).
• D+/D− → VL817 HSDn+/HSDn−. Use 33 Ω series resistors (R5/R6 on J2, R9/R10 on J3) if trace is longer than 50 mm.
• GND_DRAIN (pin 7) connects to the GND plane — keep this stub short.

ESD

• PRTR5V0U2X on D+/D− pair. For SS pairs consider a LESD5D5.0CT2G or similar ≤ 0.5 pF TVS — standard PRTR5V0U2X capacitance may be too high for SS signals.

4-Pin USB Type-A Pinout

• Pin 1: VBUS (5V, polyfuse or AP2141)
• Pin 2: D−
• Pin 3: D+
• Pin 4: GND
• Shell: GND

Routing to VL817

• D+/D− go to VL817 HSD3+/HSD3− and HSD4+/HSD4− (ports 3 and 4). Route as 90 Ω differential pair.
• VL817 SS pins for ports 3 and 4 — leave SSRX3/SSTX3 and SSRX4/SSTX4 unconnected per the datasheet. These ports are SS-capable at the IC but only wired as USB 2.0 connectors in this design.

Charging Detect (optional)

• To allow phone/tablet fast charging on USB 2.0 ports, add a BC1.2 charging port controller (e.g. TPS2514) per port. This shorts D+/D− to a specific voltage combination that tells the device to draw more than 500 mA.
• Alternatively, wire D+ to D− through 200 Ω — a simple Apple divider that allows up to 1 A on dumb chargers. Not spec-compliant but widely compatible.

ESD

• PRTR5V0U2X (SOT-363, dual-line TVS) handles D+/D− on each port. Place near connector, before series resistors.

PCB Fabrication

1. Choose a 4-layer stackup. Specify controlled impedance: 90 Ω differential on outer layers. Most fabs (JLCPCB, PCBWay) accept an impedance note in your gerbers. Standard thickness: 1.6 mm, 1 oz copper.
2. Export gerbers. Include paste stencil for QFN reflow. VL817 QFN-76L thermal pad requires stencil apertures — use 0.8× coverage to avoid solder bridging under the IC.

Soldering Order

1. Reflow U1 (VL817) first. QFN-76L requires paste on the thermal pad and reflow oven or hot-air. Inspect for bridges with a loupe — 76 pins at 0.4 mm pitch are dense. Use flux pen and solder wick to clear any bridged pins.
2. Solder passive components (caps, resistors, ferrite, polyfuse) by reflow or tweezers and hot-air.
3. Solder U2–U12 (TVS, power switches) — SOT-23 and SOT-363 packages, use flux.
4. Solder Y1 (crystal) last of the SMD parts — it's ESD-sensitive.
5. Solder connectors J1–J5 — through-hole or SMD. Check that connector shells are firmly soldered to ground pads.

Bring-Up Sequence

1. Power-on check. Without connecting USB, apply 5V to J1 VBUS via a bench supply set to 500 mA current limit. Measure 3.3V on a VCC33 pin and 1.1V on a VCC11 pin — both are generated on-chip from the 5V input. If current spikes and voltage is low, check for shorts under U1 or a bad solder joint on the LX inductor.
2. Oscilloscope check on crystal. Probe SSXI pin — should see 25 MHz sinusoid within ~50 ms of power-on. No oscillation usually means a cold solder joint on Y1 or wrong load caps.
3. Plug into a USB 3.0 host port. The hub should enumerate in under 1 second. Check Device Manager (Windows) or lsusb -t (Linux) — you should see VL817 (VID 0x2109) at USB 3.0 (5 Gbps).
4. Test each port. Connect a USB 3.0 flash drive to J2 and J3; run a speed test (CrystalDiskMark or dd). Expect 300–400 MB/s sequential for a good SS drive. Connect USB 2.0 devices to J4 and J5.
5. ESD test (optional). Discharge a 100 pF cap charged to 1 kV against the connector shell while a device is enumerated — the hub should survive and re-enumerate.

Matched pairs — most common mistake

• A length mismatch of 0.5 mm on a SS pair at 5 Gbps is already at the limit of the spec. Auto-routers almost never produce matched-length differential pairs. Always manually tune intra-pair lengths. Use your EDA tool's interactive length-matching tuning (serpentine meanders) on the shorter trace.
• Verify with the EDA DRC length-match rule: set tolerance to 0.1 mm for SS pairs, 2 mm for USB 2.0 pairs.

CC pull-downs

• Forgetting R1 or R2 (CC pull-downs) is one of the most common USB-C mistakes. Without them, USB-C PD hosts may refuse to provide power or may not negotiate an SS connection.

Crystal oscillator start-up

• If the VL817 fails to enumerate, check the crystal oscillator first — no clock means no USB. Common causes: wrong load capacitance, long traces on SSXI/SSXO, or a nearby noisy net coupling into the crystal.

QFN thermal pad continuity

• Use a multimeter in continuity mode to verify the QFN exposed pad is connected to GND through the thermal vias. A floating EP can cause erratic enumeration even if the IC appears to power up.

Impedance without fab control

• If your fab cannot guarantee controlled impedance, use an online impedance calculator (e.g. Saturn PCB Toolkit) with your stackup parameters to target 0.1 mm traces on a standard 4-layer PCB. Typical result: 90–105 Ω differential — acceptable margin for a short-trace hub board.

Ground plane splits

• If you place a slot or keep-out under a USB connector footprint (e.g. for through-hole mounting), that interrupts the return path. Use SMD connectors where possible, or ensure through-hole solder pads do not break the GND plane layer.

Per-Port Power Control

• VL817 exposes USBPEn (n=1–4) — active-high power enable outputs. Connect each to the EN input of the corresponding AP2141 power switch. High = port VBUS enabled.
• VL817 exposes USBOCn (n=1–4) — active-low overcurrent sense inputs. Connect each to the /FLAG output of the AP2141. Hub will disable the faulted port and report it to the host. Low = overcurrent event.
• Pull USBOCn pins to VCC33 via 100 kΩ if the port has no power switch (HS ports using polyfuse only). This tells the IC the port is always healthy.

VBUSDET / EXTPWRON

• VBUSDET — connect to upstream VBUS rail (after F1, 3.3V max). Hub uses this to detect host plug/unplug independently of the USB data lines.
• EXTPWRON — external power status input (3.3V max). Pull high if the hub is self-powered from an external supply; pull low (or leave low) for bus-powered designs.

Overview

• VL817 supports SMBus management from a host MCU via GPIO1/SMDAT and GPIO2/SMCLK pins (open-drain). This allows runtime control from an external microcontroller (e.g. RP2040).
• SMBus address: configurable via firmware image.

What You Can Do via SMBus

• Enable or disable individual downstream ports at runtime.
• Read per-port overcurrent status.
• Read USB link speed negotiated on each port.
• Trigger a hub reset without cycling VBUS.

If Not Using SMBus

• Leave SMBus pins unconnected or pull both high via 4.7 kΩ to VCC33.

Why the SPI Flash is Required

• VL817 loads its firmware from the SPI flash at every power-on. This flash is not optional — without it the IC will not enumerate. It also stores VID/PID, product strings, and hub configuration.
• Without a custom image, the hub enumerates with VIA Labs' default VID 0x2109, PID 0x0817, and a generic product string. This is fine for prototypes.
• A small SPI flash (e.g. W25X05CL, 512 Kbit, SOIC-8 or WSON-8) lets you store a custom VID/PID, manufacturer string, product string, serial number, and hub configuration. The VL817 reads it on every power-on.

Wiring

• CS# (chip select) — connect to VL817 USBLED4/SPICS pin.
• CLK, MOSI (SI), MISO (SO) — connect to VL817 USBLED2/SPICK, USBLED1/SPISI, USBLED3/SPISO pins respectively.
• WP# — pull to VCC_3V3 during normal operation (write-protect enabled). Pull to GND during programming only.
• HOLD# — pull to VCC_3V3 (not used in this design).
• VCC — connect to VCC33 rail. Bypass with 100 nF cap within 2 mm.

EEPROM Image Format

• The SPI flash contains a binary image with VID, PID, device release number, manufacturer string (UTF-16LE), product string, serial number, and hub configuration bytes.
• The exact memory map is defined by VIA Labs and documented in their programming tool. Do not hand-edit the binary unless you have the full specification.

Programming Methods

• Via VL817: Power the hub, connect to a Windows host, run the VIA Labs hub configuration tool. The tool programs the SPI flash over USB through the hub IC itself.
• Offline via SPI programmer: Use a CH341A or Flashrom-compatible programmer. Connect directly to the SPI flash pads (CS#, CLK, MOSI, MISO). Write the pre-built binary image.
• Via host MCU: If an MCU (e.g. RP2040) shares the SPI bus, it can program the flash at first boot from a firmware-embedded binary.

VID/PID Considerations

• You must license a VID from USB-IF ($6,000/yr) for commercial products or buy a PID under an existing VID (e.g. via OpenMoko, £10–15 one-time). Using someone else's VID is not legal for shipping products.
• For prototypes and internal use, the default VIA Labs VID 0x2109 is fine.

Bus-powered hub current allocation

Microstrip differential pair — outer layer, FR4

Uses IPC-2141A edge-coupled microstrip approximation. ±10% typical accuracy — verify with your fab's tool.

Notes

Common JLCPCB 4-layer JLC7628: H≈0.21mm, Er≈4.6. For 90Ω diff on outer layer: try W=0.1mm, S=0.1mm — confirm with their impedance table.

Parallel-resonant crystal, series circuit model

Finds C_load cap values for the SSXI/SSXO circuit. C_L is the crystal's specified load capacitance.

Notes

Formula: C_ext = 2 × (C_L − C_stray). Choose the nearest E12 value. For VL817 with a 25 MHz 12 pF crystal and ~3 pF stray per pin, 18 pF C0G caps are standard.